The present subject matter pertains to core systems and, more particularly, to write-back cache in multiprocessor systems.
Multiprocessor systems that share data require coherency of data. That is, data must be the same for all processors. For both read and write operations, data read or written must be the same, or chaos may result.
In today's modern computer systems frequently used data is often “cached”. This means that the data is stored in a fast-access cache memory instead of a relatively slower random access memory or main memory. This can introduce data coherency issues between main memory and the cache. As a result, the main memory must be updated from the cache memory. Some cache memories do not immediately write the data that has been changed back to the main memory. Cache memories that do not immediately update the main memory for changed data in the cache are called write-back cache memories.
A core may include one or more processors and one or more caches. Typically a core also includes a main memory that is slower acting as compared with the cache memories. A processor may output an address that indicates that the processor is looking for data. In a typical situation, the address is sent to the cache memory first. When the processor finds the data in the cache memory, it is called a cache “hit”. When the processor does not find the data in the cache memory, it is called a cache “miss”.
For a cache “miss” situation, a fixed-size block of data is typically obtained from the main memory and stored in the cache memory, because probabilities indicate that other data from this same block will probably be required soon.